Optimizing construction of scheduled data flow graph for on-line testability

The objective of this work is to develop a new methodology for behavioural synthesis using a flow of synthesis, better suited to the scheduling of independent calculations and non-concurrent online testing. The traditional behavioural synthesis process can be defined as the compilation of an algorithmic specification into an architecture composed of a data path and a controller. This stream of synthesis generally involves scheduling, resource allocation, generation of the data path and controller synthesis. Experiments showed that optimization started at the high level synthesis improves the performance of the result, yet the current tools do not offer synthesis optimizations that from the RTL level. This justifies the development of an optimization methodology which takes effect from the behavioural specification and accompanying the synthesis process in its various stages. In this paper we propose the use of algebraic properties (commutativity, associativity and distributivity) to transform readable mathematical formulas of algorithmic specifications into mathematical formulas evaluated efficiently. This will effectively reduce the execution time of scheduling calculations and increase the possibilities of testability

Test et Surveillance Intégrés des Systèmes Embarqués

ISBN 2-84813-071-7This report presents a summary of our research activities focusing on off-line testing and on-line supervision of embedded systems. Modern microelectronic manufacturing technologies and software tools make it feasible to integrate a complex system, into a single chip (SoC) able to hold all the components and functions that historically required a hardware board. Embedded systems made up of hardware and software generally contains a variety of integrated devices including digital, analogue, and even radio-frequency cores on the same chip. As these systems are gain sophistication, manufacturers are using them in increasingly critical applications that can result in injury, economic loss, or unacceptable inconvenience when they do not perform as required. This leads to new challenge for the test and for the real time supervision capabilities.The first part of this manuscript puts forward original BIST design methodology for analogue and mixed signal devices using embedded smart resources (embedded microprocessors and memories). The second part introduces different approaches for online supervision and discusses their applicability to online testing to of embedded ICs, including semiconcurrent and concurrent online testing strategies. It is attractive to adapt some of the results that are abundantly available in automatic control research to deal with the problem of online fault detection in electronic embedded systems. However, only some techniques are applicable to electronic systems because the design and implementation constrains are very different in both research fields. Compared to other known FDI architectures, it is shown that the model-based parity space approach is suitable for online testing of digital embedded systems with respect to electronic design constrains and allows not only for efficient fault coverage, but also for efficient implementation facilities.Ce document est rédigé en vue de l'obtention d'un diplôme d'habilitation à diriger des recherches de l'Université Joseph Fourier de Grenoble. Il présente une synthèse de nos travaux de recherche concernant essentiellement le test hors ligne et la surveillance en fonctionnement des systèmes embarqués. Ces travaux sont conduits au sein du laboratoire TIMA de Grenoble successivement dans les équipes ‘'RIS'' (Reliable Integrated Systems) jusqu'en 2002 et ‘'RMS'' (Reliable Mixed Signal Systems) de 2002 à ce jour.Dans le chapitre introductif, nous définissons les systèmes embarqués et nous présentons les défis scientifiques et techniques qu'induisent leur émergence et leur prolifération rapides. Ensuite, nous posons le problème du test hors ligne et de la surveillance en ligne de ces systèmes. La fin du chapitre situe nos activités dans la discipline du test des systèmes intégrés et présente nos principaux axes de recherche. Dans le chapitre 2, nous présentons nos travaux concernant le test intégré de modules analogiques et mixtes incorporés dans un environnement numérique. La première partie du chapitre est consacrée au développement d'outils de conception assistée par ordinateur pour le test des systèmes analogiques et mixtes alors que la deuxième décrit les techniques d'intégration de test à bas coût que nous avons développées pour les systèmes analogiques et mixtes. Le chapitre 3 concerne les techniques de surveillance en ligne intégrée. Une description rapide du flot de synthèse automatique de systèmes intégrés nous permet de situer nos travaux par rapport aux processus modernes de conception de circuits. Les méthodes de test en ligne non-concurrent, semi-concurrent et concurrent sont ensuite exposées. Nous expliquons les liens que partagent les techniques proposées avec d'autres disciplines de recherche, notamment les travaux sur la détection et l'identification de fautes dans les systèmes automatisés. Le chapitre 4 conclut le mémoire. Nous indiquons aussi quelques perspectives possibles pour nos prochaines activités de recherche. Les pistes qui se dégagent concernent aussi bien la poursuite des travaux déjà engagés que des travaux sur de nouvelles problématiques

Embedded Test and Control of Analogue/RF Circuits Using Intelligent Resources

Invited embedded tutorialInternational audienc

Optimal Detector Design for On-line Testing of Linear Analog Systems

The design of integrated fault detector for on-line testing of linear analog systems is discussed in this paper. The method consists in a concurrent processing of available the node voltage signals to provide a residual on-line, that carries information about the faults. Contrary to the few previous works dealing with the particular case of state variable analog systems, the method proposed here is useable without limitation for a larger class of linear analog systems, even when the state variables are not available as measurable voltages. For this purpose, an algorithm providing an extended state space model for any linear analog system from its netlist description is developed and implemented

Residual checking method for concurrent fault detection in linear analog systems

International audienceA generalised model based strategy for on-line testing of linear analog systems is discussed in this paper. The method consists in a simple processing of input-output signals to provide a residual signals that carries information about the faults. The inherent redundancy contained in the static and dynamic relationships among the system in input and measurable signal is exploited for this goal. In this paper, the use of extra circuitry with the objective of concurrent fault detection is extended to a larger class of linear analog systems. The detection dedicated circuitry remain comparable to the previous approach dealing with the particular class of state variable systems

Application of NARMAX modelling to eddy current brake process

ISBN: 0780325508In this paper, we define an approximate theoretical model, describing the behaviour of an eddy current disc brake in the low speed zone. It is made use of the nonlinear autoregressive moving average with exogenous inputs modelling (NARMAX) to build a polynomial nonlinear model for eddy current braking process. The identification method is based on the difference equation approximation of an input-output map. Only the input-output information are required for the estimation procedure

Analytical redundancy based approach for concurrent fault detection in linear digital systems

ISBN: 0769506461With the advent of VLSI technology, large numbers of processing elements which cooperate with each other to achieve a complex function have become feasible. A major concern in the design of these complex devices has been the ability to verify and in some instances guarantee their fault free operation. Since any error in processed data may have catastrophic effects, therefore some levels of fault detection must be incorporated in order to increase the reliability of systems. This paper presents a general method for concurrent error detection in linear digital systems using analytical redundancy, i.e., relations between the measured variables. The fault detection mission can be performed using only the available connectable (measurable) variables, e.g. the external inputs and outputs, while the hardware overhead of the test circuit can be optimized through connecting on some internal mensurable state variables. Generally, this method is applicable to all linear digital systems while the test circuit obtained for on-line detector implementation is still very reasonable

High level synthesis methodology for on-line testability optimization

ISBN: 0769506461Introducing testability considerations as soon as possible in the design process results in more testable design with reduced area overhead. A very important improvements can be carried out before the scheduling step. An optimization which takes effect at behavioral specifications and leads to production of an improved scheduling is proposed by this study. This optimization is good for improving not only on-line testability but also for some other objectives in the obtained synthesis